New to SV

Randomisation & overconstrained classes

jiperna — Fri, 09 Jul 2010 09:29:48 GMT

Hello,

I am trying to determine whether a set of dynamic constraints (i.e., they are based on a couple of state variables that may change during simulation) I have placed inside a class in my testbench is over-constrained.

The only solution I have found so far is to invoke randomize() and test for its result but this produces a lot of "over-constrained class" output that I don't want.

Is there a different function I can call to check whether the class is over-constrained?

Another alternative I was considering (but so far unsuccessful) would be to re-direct the output temporarily to /dev/nul while I call randomize() and then restore it to stdout. Is there a way of doing this in SystemVerilog?

Any other suggestions/ideas would be greatly appreciated.

Cheers,

Juan

Generalized code for varied DATA_WIDTH parameter

ajit.myth — Thu, 04 Mar 2010 02:04:01 GMT

How to generalize the data access for all possible data width (parameter DATA_WIDTH) for the following code:

logic [DATA_WIDTH/2-1:0] d_pos[0:3];
logic [DATA_WIDTH/2-1:0] d_neg[0:3];
logic [DATA_WIDTH-1:0] wdat[0:3];

for (int i=0; i<4; i++) begin
fork
begin:U0
@posedge clk;
d_pos[7:0] = m_if.dat[7:0] ; //dat is IF port
@negedge clk;
d_neg[7:0] = m_if.data[7:0];
end
begin: U1
@posedge clk;
d_pos[15:8] = m_if.dat[15:8] ; //dat is IF port
@negedge clk;
d_neg[15:8] = m_if.data[15:8];
end

begin:U2
@posedge clk;
d_pos[7:0] = m_if.dat[23:16] ; //dat is IF port
@negedge clk;
d_neg[23:16] = m_if.data[23:16];
end
begin: U3
@posedge clk;
d_pos[31:24] = m_if.dat[31:24] ; //dat is IF port
@negedge clk;
d_neg[31:24] = m_if.data[31:24];
end
join
wdata= {d_neg,d_pos};
end //end of for loop

Now, the above work for DATA_WIDTH = 64. But if the parameter is changed to 128 or 144 or any other value, then the number of threads to be spawned inside fork-join will increase. For eg, for DATA_WIDTH=128, 8 threads (U0 - U7) need to be explicitly written.

Can we somehow generalize this code for all possible DATA_WIDTH parameter value?

Strings

daylitemoon — Sun, 13 Sep 2009 15:12:29 GMT
Hi Friends,
I'm new with SystemVerilog and need your help. I'll try my best to explain what I want to do.
I have a string variable that is holding a path pointing to a module that contains different Ages (with Names as fields), for example,

string namesPath = "top.people.";
foreach(age[j]) begin
----
----
end

I will select an age (on each loop iteration) from the queue "age" and then randomly select a name under the selected age. I want to place this age and name at the end of the path "namesPath" to get to the name (and do some operation on it).

A complete namesPath should look like this format,
top.people.ten_nancy
where, the selected age was "ten" and random name was "nancy".

Can you please suggest how this can be accumplished?
Please reply asap.

Thanks!!

SV Assertion Example

yitolin — Fri, 10 Oct 2008 12:09:37 GMT
Hello,

I am new to SV and i was going through a very simple example in design and assertion techniques in SV. I have made 3 modules, clkgen, counter2 and top (where i call the counter and clkgen modules and run the simulation from) and i am using QuestaSim 6.3c to create and run the simulations. I have created a sequence, property and asserted the property but i get an error when i try to compile and simulate the top design. The error is "The sva directive is not sensitive to a clock. Unclocked directives are not supported." The sequence, however, is being stimulated (sensitive) by a clock so i don't quite understand what i am doing wrong. Here is the code to my top design

module top;

/* Make a reset that pulses once. */
reg reset = 0;
initial begin
# 17 reset = 1;
# 11 reset = 0;
# 29 reset = 1;
# 11 reset = 0;
# 2500 $stop;
end

wire [7:0] value;
wire clk;
logic [7:0] overflow = '1;

clkgen1 clk1 (clk);
counter2 c1 (value, clk, reset);

/* sequence s1;
@(posedge clk) value === overflow;
endsequence

property p1;
not s1;
endproperty */

a1 : assert property(not (@(posedge clk) value === overflow));

initial $monitor("At time %t, value = %h (%0d)",
$time, value, value);
endmodule // top

The commented out sequence s1...is what i originally had and so i decided to try the assert method another way. I am just trying to get an idea of how the assertion statements work by testing to see if the counter ever overflows (which it does) and what the simulator tells me when this assert statement fails when it does.
I have been reading "A practical Guide for SystemVerilog Assertions" and i feel i have made the calls correctly, but i might be missing some things because i am new Can anyone help me with this problem? Is there something i am missing?

Thank you all so much.

Hector

How to see class properties in vcs

Rohit — Wed, 27 Jun 2007 03:05:47 GMT

Hi ,

I am new to system verilog and using classes in my current project .

Right now , to see class properties i am assigning it to some debug signal or using $display .But this is very tedious .

So , please let me know how to view the class variables in tools like VCS .

Regards

Rohit

Any equivalent of AHB eVC in system verilog

danyuk7 — Wed, 09 May 2007 09:15:16 GMT

Hi,

I am new to this user group. Good to be part of this group.

I would like to know if any verification component is available in System Verilog similar to AHB eVC in specman.

Thanks in Advance.

Rgds,

Dan

An Example to Learn SystemVerilog

dblore — Wed, 02 May 2007 07:43:02 GMT

In specman there is an example used to learn e usage "sbt_router". Is there any such example in systemverilog?

Is there any website where a sample project using systemverilog is explained?

Thanks.

Original Post: prathishnair

forum admin — Fri, 27 Apr 2007 17:21:09 GMT
hi friends, I am new to system verilog and would anyone please tell me which are some of the good books to refer for learning system verilog.