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 SVUG Community Forum
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Messages |
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ANSHUMAN
Posts:3
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| 12/15/2008 2:49 PM |
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Hi,
I have created some assertions in a separate module and now I am trying to bind these assertions to the RTL using the bind command. The assertions are not related to a single module but spans many module.
For eg: Assertion 1 is for RTL module 1 and another assertion is for another RTL module 2.
I read that the bind command can also use hierarchical path references while connecting ports. But, when I try to do this, I get the following error:
Error-[XMRE] Cross-module reference resolution error
Cross module resolution failed, token 'RqCamWrIndx1'. Originating
module 'LsuI', first module hit 'LsuI'.
Eg:
RTL Hierarchy:
module Chip
LsuI Lsu (
);
endmodule
module LsuI
RoqI Roq
(port1, port2, port3); //Instantiating Roq
endmodule
module RoqI (port1, port2, port3)
endmodule
//assertion module
module assertion (port1, port2, port3)
//assertions written here
endmodule
module top
bind LsuI assertion myassert (
LsuI.Roq.port1,
LsuI.Roq.port2,
LsuI.Roq.port3
);
endmodule
1) Chip instantiates Lsu, which in turns instantiates Roq (that has all the ports)
2) assertion module is the one that I want to bind to LsuI, but the assertions inside are for different modules inside LsuI
3) Hence, using bind command, connected assertion to LsuI module but the ports were coming deep from the hierarchy. This is where I am getting the error.
Any help would be appreciated.
- Anshuman
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SHALOM
Posts:43
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| 12/16/2008 1:56 AM |
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The hierarchical signal names need to be as seen from module top or full hierarchical names. In this case, Chip.Lsu.Roq.port1, for example.
Shalom Bresticker |
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