 |
|
|
|
|
|
|
|
|
|
|
|
|
 SVUG Community Forum
|
|
| Author |
Messages |
|
NEIL
Posts:2
 |
| 05/20/2008 9:52 AM |
|
I see in the Doulos SystemVerilog Golden reference guide that procedural continuous assignments are deprecated.
I have some USB verification IP which relies on assigning different drive strengths to the dp/dm signals depending on
what symbol is being sent (or received). I can't see a reasonable way to model this apart from using a number
of procedural continuous assignments. Any suggestions please?
Regards, Neil
|
|
|
|
|
SHALOM
Posts:42
|
| 05/20/2008 12:01 PM |
|
They are not actually deprecated, just considered for deprecation. In practice, all simulators support them and will continue to support them. They are not going to be deprecated in the next revision of the IEEE SV standard either.
Shalom.Bresticker@intel.com |
|
|
|
|
|
| You are not authorized to post a reply. |
|
|
|
ActiveForums 3.7
|
|
|
|
|
|
|
|
|
|
|
|
|
 |
|