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 SVUG Community Forum
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SANDEEP
Posts:2
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| 05/16/2008 1:28 PM |
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If you have used RVM (Reference Verification Methodology) in Vera or VMM (Verification Methodology Manual), AVM (Advanced Verification Methodology) or OVM (Open Verification Methodology) in SystemVerilog, then you will be familiar with rvm_env, vmm_env, avm_env, etc. base classes. These classes has set of methods build, cfg_dut, run, etc. which are getting called in predefined order. When you call any single method, it will make sure that previous methods in given order set has already called, and if not, it will be called first to ensure ordering.
Do you know how this order can be maintained in *_env (rvm_env, vmm_env, avm_env or ovm_env) classes?
Read this article, to know one way of implementing this chain of method calls.
Thanks,
Sandeep B Vaniya
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