 |
|
|
|
|
|
|
|
|
|
|
|
|
 SVUG Community Forum
|
|
| Author |
Messages |
|
SAMEER
Posts:3
 |
| 03/09/2009 9:16 AM |
|
Hi,
Being a student of VLSI, I would like to know if there are any free tools to learn system verilog!
Does the student version of Modelsim support system verilog? If so, Can i use the VMM libraries with the student version?
Are there any better tools?
Thanks in advance.
Kaushik. |
|
|
|
|
SERGEY
Posts:12
|
| 03/09/2009 5:20 PM |
|
there are several points to notice: Mentor has 2 simulators - one is QuestaSim the other is ModelSim.
ModelSim is a reduced version of QuestaSim in SV functionality support. ModelSim mainly lacks for assertions, and constraint randomization, so the stuff in VMM that requires those things won't work in ModelSim.
The next point is that there are two main verification libraries/methodologies. they are VMM by Synopsys and OVM by Mentor. Although they both told to be compatible with the SV standard, the simulators from those two vendors are not, i.e. they have minor difference in interpretation of some language aspects. All in all it is told by the guys on forums that Synopsys' VMM goes better on the Mentor's QuestaSim than Mentor's OVM on Synopsys'. So I would advice you to try OVM as far as you already have ModelSim, or ask someone in your Uni if they have some agreement with Synopsys, or apply directly to Synopsys/Mentor and ask for some trial/education versions of their tools for they should be interested in expanding future markets for thier products.
Regards |
|
|
|
|
|
| You are not authorized to post a reply. |
|
|
|
ActiveForums 3.7
|
|
|
|
|
|
|
|
|
|
|
|
|
 |
|