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 SVUG Community Forum
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David
Posts:2
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| 08/28/2008 6:07 PM |
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just read "Systemverilog for design", try to compile its last example "10.00.00_example_top.sv". which is downloaded from http://www.sutherland-hdl.com/books-by-sutherland.php.
I use syplify pro 9.2. but seems to me it can't complie this example.
it can't identify union.
I am new to system verilog. is it widely used by design engineer? I think it will take a while to get popular.
guess it is only used by verification.
could anyone tell me how many tools could synthesis systemverilog. which is most popular.
thanks.
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Shalom
Posts:11
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| 08/28/2008 10:12 PM |
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Those downloadable examples are from the first edition of the book, which was based on SV 3.1a, and in many cases are no longer valid in IEEE 1800-2005. The code examples in the second edition of the book were updated to the IEEE version, but are not downloadable.
Shalom.Bresticker@intel.com |
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David
Posts:2
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| 08/29/2008 11:35 AM |
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thanks.
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