hi ,

I`m new to system verilog. Right now I`m have to be familiar with SV from design and synthesis perspective. I read in Sutherland`s book that functions,task inside package can be synthesizable if prerfixed as automatic and should not contain static variable. But , when I tried to read it using Synopsys Design Analyzer(synopsys 2006.06-SP3), it says unknown construct `package`and therefore will be ignored.

I want to know if contents of package are synthesizable , if yes , why Design Analyzer is ignoring it?


Please help me in this .


Thanks in advance.
--Abhijit