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 SVUG Community Forum
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| Author |
Messages |
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Sandeep
Posts:2
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| 04/23/2008 5:52 AM |
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Hi,
Following is the excerpt from SystemVerilog LRM about important features of define macro.
1. In Verilog, the ‘define macro text can include a backslash ( \ ) at the end of a line to show continuation on the next line.
2. In SystemVerilog, the macro text can also include `", `\`" and ``.
An `" overrides the usual lexical meaning of ", and indicates that
the expansion should include an actual quotation mark. This allows
string literals to be constructed from macro arguments.
A `\`" indicates that the expansion should include the escape sequence \", e.g.
`define msg(x,y) `"x: `\`"y`\`"`"
This expands:
$display(`msg(left side,right side));
to:
$display("left side: \"right side\"");
3. A `` delimits lexical tokens without introducing white space, allowing identifiers to be constructed from arguments,
`define foo(f) f``_suffix
This expands:
`foo(bar)
to:
bar_suffix
Using these three simple features you can create generic/reusable
components in SystemVerilog. Synopsys has widely used these features in
their vmm for SystemVerilog library. Recall `channel, `atomic_gen and
`scenario_gen macros of vmm.
To know details of Advanced use of these features and how it is used in VMM, please read this article.
Thanks,
Sandeep |
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