Hi Everyone,

    I have a query for you all.

We are developing a Verification IP  in System verilog

We are trying to Call a task from a Class.

The task is defined inside a module.

But the Class is define outside the module.

So we are using an interface to call the task from the module and map it to the class.

An example piece of code which we are using is as follows:-

______________________________________________

interface req_gen_oop();

   task call_req_gen;

      input logic Δ:0] Tlp_type;                      

      gpex_bfm_tb.gpex_bfm_inst.req_gen(Tlp_type);

   endtask

endinterface

program test(req_gen_oop req_gen_test);

         Environment env;

         env = new(req_gen_test);

endprogram

______________________________________________

We are getting the following error when the desing is loaded.

# ** Fatal: (vsim-3695) test.sv(0): The interface port 'req_gen_test' must be passed an actual interface.

#    Time: 0 ns  Iteration: 0  Instance: /test File: test.sv

# FATAL ERROR while loading design

# Error loading design

Kindly let us know on how shall we proceed further.

Thank you,

Karthick.G