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 SVUG Community Forum
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PRANEET
Posts:3
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| 12/26/2007 4:39 AM |
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Hi All,
using a user-defined data type for "wire" data type is not supported in system verilog
any thoughts on what could be the reason for that..?
Thanks,
Praneet |
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DIVYESH
Posts:6
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| 01/08/2008 3:36 AM |
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Hi Praneet,
As per my understanding , according to SystemVerilog LRM.
typedef has syntax for user defined data types as below.
"typedef data_type type_identifier variable_dimension ;"
Also wire is not a "data type" but net_type.
So, "typedef wire" is not supported
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Thanks & Regards
Divyesh Gajjar
eInfochips ltd.
www.einfochips.com |
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PRANEET
Posts:3
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| 01/09/2008 2:19 AM |
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hi Divyesh,
if Iam not wrong data types in Verilog are divided into two main categories - register data type and net data type.
so
the syntax "typedef data_type type_identifier variable_dimension ;"
should mean that wire can be used with typedef
also i don't think there is anything specific in Sys-Vlog LRM that says wire is not a data type or it cant be used with typedef
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DIVYESH
Posts:6
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| 01/09/2008 3:37 AM |
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Hi Praneet,
Please refer System Verilog 3.1a LRM topic 3.2 Data type syntax.
from this syntax table you can find values under data_type, which does not include net_type.
Please let me know after refering if my understanding is wrong.
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Thanks & Regards
Divyesh Gajjar
eInfochips ltd.
www.einfochips.com |
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DIVYESH
Posts:6
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| 01/09/2008 10:33 PM |
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Look at the thread beginning at http://www.eda-stds.org/sv-ec/hm/5399.html
and see if that answers your question.
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Thanks & Regards
Divyesh Gajjar
eInfochips ltd.
www.einfochips.com |
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PRANEET
Posts:3
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| 01/09/2008 11:26 PM |
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hi divyesh
lrm has got "net_type" under data type section.
i looked at the thread, it doesn't have anything conclusive..
well may be we will see support for "typedef wire.." in future
--Praneet |
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