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Subject: constraints hireacrchy
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TalUser is Offline

Posts:1

12/11/2007 3:31 AM  

In my environment I'm dealing with network topology, first terminnoogy:
The Verification Environment composed of DUT,Channels,Connections - each connection transmits packets via channels to the DUT.

The problem is how to control the packet attributes(i.e, pkt_color, pkt_size) in a flexiable way.
I take those attributes as an simplified example.

I would like to constraine those attributes by hirearchical constraints, I hope  the example below clarify the problem:


//Testcase test_1 (two hirearchies only)

//Topology: 1 channel, 3 connections{0,1,2}
//All packets(exclude connection #0 are constrained according to:
//   pkt_size dist {100:=1,𖒤:500]/=5, 1000:2}
//   pkt_color dist {GREEN:=19, RED:=1}
// Connection #0 packets are constrained according to:
//   pkt_size dist {500:=1, 1500:2}
//   pkt_color dist {GREEN:=1, RED:=0}

constraint connection::pkt_size_C
 {
   pkt_size dist {100:=1,𖒤:500]/=5, 1000:2}
   pkt_color dist {GREEN:=19, RED:=1}
 }

constraint connection::connection_global_c                     //why cant I use if(..)begin..end block  (Questa 6.2ie)
 {
         if (con_id==0) 
            pkt_size dist {500:=1, 1500:2}
         if (con_id==0) 
            pkt_color dist {GREEN:=1, RED:=0}
  }




Output    

<0>  gen_pkts: con_id #0 Generates 3 Packets
# <0>  printme: Packet generated - pkt_size=500
# <0>  printme: Packet generated - pkt_size=1500
# <0>  printme: Packet generated - pkt_size=1500
# <0>  gen_pkts: con_id #1 Generates 3 Packets
# <0>  printme: Packet generated - pkt_size=100
# <0>  printme: Packet generated - pkt_size=350
# <0>  printme: Packet generated - pkt_size=1000
# <0>  gen_pkts: con_id #0 Generates 3 Packets
# <0>  printme: Packet generated - pkt_size=500
# <0>  printme: Packet generated - pkt_size=700
# <0>  printme: Packet generated - pkt_size=650

DivyeshUser is Offline

Posts:6

01/28/2008 1:10 AM  
Hi Tal,

As per my understanding problem you face is changing of constraints for channels as per your need..
see below example if it helps you.

constraint connection::pkt_size_C
{
(constraint_change == 0) ->pkt_size dist {100:=1,𖒤:500]/=5, 1000:2};
(constraint_change == 0) -> pkt_color dist {GREEN:=19, RED:=1};
(constraint_change != 0) -> pkt_size dist {500:=1, 1500:2};
(constraint_change != 0) -> pkt_color dist {GREEN:=1, RED:=0}
}

by using above constraints you can pass con_id for the constraints you want for channel by just chaning the variable constraint_change.


I hope this solves your issue .

Please let me know if my understading of problem is wrong.



Thanks & Regards
Divyesh Gajjar
eInfochips ltd.
www.einfochips.com
JasonUser is Offline

Posts:7

01/29/2008 2:18 AM  
Hi Tal

Let me add a couple of things to the previous reply:

1. if-else blocks. It's a bit wierd, but in a constraint block you use curly brackets instead of begin-end.
The thing you are trying to encapsulate is a constraint block (denoted by curlies), not a procedural statement.

if (con_id==0) {
   pkt_size dist {500:=1, 1500:2}
   pkt_color dist {GREEN:=1, RED:=0}

} else {
...
}

2.  Flexibility. I'm not really sure what your goals are here. There are a couple of things to remember though:

There are no default contraints in SystemVerilog.

This means whatever you define in your base class has to be a loose enough constraint so that future constraints will not clash with it. They can of course further constrain the values. Alternatively, the constraint(s) should be grouped logically in a way that they can be disabled easily. This can can be using another variable, or disabling the constraint block they are in.

This also means that if you DO NOT have a constraint defined, the values will randomize to their limits. E.g.

Statements like this:

(cond_id == 0) -> pkt_color dist {GREEN:=1, RED:=0};

results in no constraint for pkt_color if cond_id != 0.


Jason

--
jason.sprott@verilab.com
www.verilab.com

DivyeshUser is Offline

Posts:6

01/29/2008 9:30 PM  
Hi Jason,
You are right for below statement.

"Statements like this:

(cond_id == 0) -> pkt_color dist {GREEN:=1, RED:=0};

results in no constraint for pkt_color if cond_id != 0."

That is the reason of keeping constraint.
(cond_id != 0) -> pkt_color dist {GREEN:=1, RED:=0};

so that out of above two only one will be hit for every condtion as per requirement.

Please do correct me if I am wrong.

Thanks & Regards
Divyesh Gajjar
eInfochips ltd.
www.einfochips.com
JasonUser is Offline

Posts:7

01/29/2008 11:39 PM  
Divyesh

You're absolutely right. There was nothing wrong with your example at all. My intention was to highlight the sometimes misunderstood nature of constraints.

Apologies for the confusion.

Jason

--
jason.sprott@verilab.com
www.verilab.com
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