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 SVUG Community Forum
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Meng-Yuan
Posts:5
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| 07/31/2010 2:18 AM |
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| I want to suggest a feature for the future release of SystemVerilog, however, I don't know where I can propose the feature. I post the feature here. If this post made someone unhappy, please excuse me.
The feature is that: is it possible for SystemVerilog supports "Module Inheritance" ability?
If SystemVerilog supports Module Inheritance,
we maybe able to reuse the module.
For example, the following is a pseudo SystemVerilog code:
---------------------------------
module Cat;
enum logic Ώ:0] {grey, orange} color;
endmodule
module Tom (output finish, input mouse) extends Cat;
// See http://en.wikipedia.org/wiki/Tom_and_Jerry
assign color = gery;
EatMouse eatMouse(finish, mouse);
endmodule
module Garfield extends Cat;
// See http://en.wikipedia.org/wiki/Garfield
assign color = orange;
endmodule
---------------------------------
Tom and Garfield modules reuse Cat module.
These reuses are meaningful, because
Garfield doesn't eat mouse.
Without Module Inhertanince ability, we have to
combine all codes into a module and use "Generate If" to make a decision of the kind of a cat. On the other word, we might only write:
---------------------------------
module Cat(output finish, input mouse);
parameter kind;
enum logic Ώ:0] {grey, orange} color;
if(kind == 0) begin // Tom.
assign color = gery;
EatMouse eatMouse(finish, mouse);
end
else begin // Garfield.
assign color = orange;
end
endmodule
---------------------------------
This code is quiet ugly compared with the "Module Inheritance" one and very difficult to maintain. And the IO ports "finish" and "mouse" is meaningless for Garfield.
Is it possible for "OOP for module"? |
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Meng-Yuan
Posts:5
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| 07/31/2010 2:22 AM |
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| I' sorry. I don't know why the newline characters are dropped in my post. |
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Meng-Yuan
Posts:5
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| 07/31/2010 2:30 AM |
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I want to suggest a feature for the future release of SystemVerilog, however, I don't know where I can propose the feature.
I post the feature here. If this post made someone unhappy, please excuse me.
The feature is that: is it possible for SystemVerilog supports "Module Inheritance" ability?
If SystemVerilog supports Module Inheritance, we maybe able to reuse the module.
For example, the following is a pseudo SystemVerilog code:
---------------------------------
module Cat;
enum logic [ 1:0] {grey, orange} color;
endmodule
module Tom (output finish, input mouse) extends Cat;
// See http://en.wikipedia.org/wiki/Tom_and_Jerry
assign color = gery;
EatMouse eatMouse(finish, mouse);
endmodule
module Garfield extends Cat;
// See http://en.wikipedia.org/wiki/Garfield
assign color = orange;
endmodule
---------------------------------
Tom and Garfield modules reuse Cat module. These reuses are meaningful, because Garfield doesn't eat mouse.
Without Module Inhertanince ability, we have to combine all codes into a module and use "Generate If" to make a decision of the kind of a cat.
On the other word, we might only write:
---------------------------------
module Cat(output finish, input mouse);
parameter kind;
enum logic [ 1:0] {grey, orange} color;
if(kind == 0) begin // Tom.
assign color = gery;
EatMouse eatMouse(finish, mouse);
end
else begin // Garfield.
assign color = orange;
end endmodule
---------------------------------
This code is quiet ugly compared with the "Module Inheritance" one and very difficult to maintain.
And the IO ports "finish" and "mouse" is meaningless for Garfield.
Is it possible for "OOP for module"?
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Meng-Yuan
Posts:5
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| 07/31/2010 2:32 AM |
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| I post the article again after fixing the newline character problem. |
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SHALOM
Posts:47
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| 08/01/2010 5:49 AM |
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This is under work for the next version of the Standard. See http://www.eda-stds.org/mantis/view.php?id=1356 and http://www.eda-stds.org/mantis/view.php?id=2997.
Shalom |
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Meng-Yuan
Posts:5
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| 08/01/2010 6:00 AM |
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Hello, Shalom:
Thank you for your reply.
However, what feature I propose is "Module Inheritance" instead of "Multiple Inheritance."
"Multiple Inheritance" is used for "class,"
but "Module Inheritance" is used for "module (or interface)."
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SHALOM
Posts:47
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| 08/01/2010 6:02 AM |
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Oops. Sorry for not reading carefully.
Shalom |
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| You are not authorized to post a reply. |
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