The DUT in my testbench has a pci port with a lot of bidirectional signals. If I define the signals within the interface clocking block as inout or output, I get a compile error from VCS saying that a clocking block output cannot be connected to an inout port. The LRM doesn't seem to address this issue.

BTW, I don't know if it matters, but I am using hierarchical references to the clocking block wire in the DUT instantiation because the DUT has no interfaces defined (regular verilog module).

How do I make the compiler happy and allow either the transactor or the DUT drive these signals through the interface?