RegisterLogin  
Update Profile
   
You are here: Forum  
Minimize 
SVUG Community Forum
Subject: Array of interface issue
Prev Next
You are not authorized to post a reply.

Author Messages
AkshayUser is Offline

Posts:5

04/08/2010 12:11 AM  
Hi, i want to make interface array. my interface have one input signal clock. how can i make array of this interface and pass clock as input? can any one help me with example and syntax? Thanks for your time in advance. Regards, Akshay
KeithUser is Offline

Posts:6

04/09/2010 12:17 PM  
I think you can do it like this:

ifc_reg_bus rex_reg_bus_arrayΐ] (xusb_clk);

interface ifc_reg_bus (input bit clk);
endinterface

This should instantiate 2 interfaces with names rex_reg_bus_arrayΎ] and rex_reg_bus_arrayΏ] both with the clock connections to xusb_clk.

AkshayUser is Offline

Posts:5

04/12/2010 6:51 AM  
Hi, Thanks a lot for your help and time.
You are not authorized to post a reply.
Forums > General Discussion > Main Discussion Area > Array of interface issue



ActiveForums 3.7
  

 Copyright 2008 by SystemVerilog User Group Contact Us    Privacy Statement