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NOO8Y
Posts:2
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| 03/09/2010 4:44 AM |
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Hello everyone,
I'm just learning SV, for school purpose with few HDL background  I had some question I couldn't answer on Internet... I hope you'll agree to give me some help.
I have two main verilog modules A and B. and also memory modules : Mem1 and Mem2
I want to do a testbench for A.
A communicates with Mem1 / Mem2 / B and is not the top level. So it has some inputs / outputs.
I want to use interface for my testbench (the RTL A doesn't use any)
So here is what I had in mind :
Creating 3 interfaces : Intf_Mem1_A ; Intf_Mem2_A and Intf_B_A
Creating a module A_with_interface that would instanciate the current A and connect it pin by pin to the interfaces
i.e
module A_with_interface // In SV
(
input clock,
output svug, // ;-)
// Other inputs / outputs of A that are not related with Mem1 / Mem2 / B
Interface Intf_Mem1, // Encapsulate communication between A and Mem1
Interface Intf_Mem2, // Encapsulate communication between A and Mem2
Interface Intf_B // Encapsulate communication between A and B
);
// Instanciate A (in verilog) and connect it to the interfaces
A mymodule(
.clk (clock),
.mem1_req(Intf_Mem1.req),
// ...
.mem2_req(Intf_Mem2.req),
// ...
.B_data(Intf_B.data),
// ...
);
endmodule // End of module A_with_interface
My question is : Is the philosophy of interfaces in SV like what I had in mind ? or is it something else, for example creating one single interface for A, and into it, nested interface for B, Mem1 and Mem2
something like :
interface Intf_A(
// Some shared nets
);
// Inputs / outputs not related to Mem1 / Mem2 / B
interface Mem1();
//...
endinterface
interface Mem2();
//...
endinterface
interface B();
//...
endinterface
endinterface
I believe this way of doing is more logical, but I'll have thousands of lines in one file and I hate that !
Last question : For my testbench, many signals will be fixed ( to '1, '0 and 'z)
Should I anyway connect all the signals to the interface, then initialze them, or is there a way to connect directly to '1, '0 or 'z in the interface
something like :
module A_with_interface // In SV
( ...);
// Instanciate A (in verilog) and connect it to the interfaces
A mymodule(
.clk (clock),
.mem1_req(Intf_Mem1.req),
.config01 (Intf_Mem1.1'b0) <-- This doesn't work, but is what I mean
// ...
.mem2_req(Intf_Mem2.req),
// ...
.B_data(Intf_B.data),
// ...
);
endmodule // End of module A_with_interface
I believe it's much more logical to connect every signals to the interface, and then do an initialization task, but then I'll have thousands of lines in one file (and again : I hate that !)
Thank you for your help
PS : No way to insert code in posts ?!
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Vaibhav
Posts:6
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| 03/11/2010 3:28 AM |
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Hi,
As you are saying you have four different verilog modules, have four different interfaces (like intf_a, intf_b, intf_mem1, intf_mem2) each for one module.
interface intf_a();
// Signals of verilog module a
endinterface : intf_a
interface intf_b();
// Signals of verilog module b
endinterface : intf_b
interface intf_mem1();
// Signals of verilog module mem1
endinterface : intf_mem1
interface intf_mem2();
// Signals of verilog module mem2
endinterface : intf_mem2
The signals which will remain the '1, '0 or 'z do not add those signals
in the interfaces (this will reduce your line of code.). While taking
instance of module you can bind those signals to the respective '1, '0,
'Z values in below manner:
A mymodule(
.clk (clock),
.mem1_req(Intf_Mem1.req),
.mem1_en(1'b1),
............
............
);
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NOO8Y
Posts:2
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| 03/11/2010 6:39 AM |
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Hello,
Thank you for your help, having one interface per module sounds nice, and modports would help to distinguish with which module the communication happens.
But I was wondering if having one interface per module connected to isn't a better solution ?
If A communicates with B and C, and I want to create the top level :
With your idea, I would have three interfaces A_if, B_if and C_if, but the wires between A, B and A, C are not connected yet.
To connect A and B for example, I'll need to create modports : A_if.Bpart and B_if.Apart
And then connect wires of A_if.Bpart to wires of B_if.Apart
But if I have one interface per module you communicate with, i'll have for A:
A_C_if // interface between A and C
A_B_if // interface between A and B
This way, I connect wires of A and B directly to one interface
With your solution, I create two interfaces, and connect the interfaces between themselves.
What do you think ? |
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Vaibhav
Posts:6
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| 03/11/2010 7:23 AM |
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Hi,
Yes. you are correct....
This way, I connect wires of A and B directly to one interface
With your solution, I create two interfaces, and connect the interfaces between themselves.
I will prefer to have different interfaces for each module. So here same interface you can use to connect your model with any other VIP/DUT.
Thanks,
Vaibhav |
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