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 SVUG Community Forum
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| Author |
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Gaurang
Posts:7
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| 03/04/2010 9:23 AM |
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| Hello everyone,
I have a VHDL design which has few VHDL component instantiations.
Say, VHDL_TOP --> (COMP1_VHDL, COMP2_VHDL, COMP3_VHDL)
In the lower level instance, I have a variable.
If I use Verilog convention, I can refer to that variable as "VHDL_TOP.COMP2_VHDL.my_reg"
Now I want access this variable in my SV test bench which instantiates design top VHDL_TOP.
How can I access this variable?? Can I do it without modifying any part of my design?
If it was a port in design top or even if it would have been very easy to bind it using a dummy module. (I want tool independent solution!)
Waiting for reply...
Gaurang |
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