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 SVUG Community Forum
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William
Posts:5
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| 02/24/2010 8:04 AM |
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In a code in sv, I need to do basic math operations (+, -, * and /) with decimal numbers.
Example:
- x=a+0.2;
- y=a-0.2;
- z=b+14.4;
- w=c*255, with 0
But when I try to simulate it, the numbers are automatically truncated , and I really need the decimal part.
Is there any way to solve this situation?
Thanks!
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SHALOM
Posts:43
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| 02/24/2010 1:37 PM |
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Declare your variables as real.
Shalom Bresticker |
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William
Posts:5
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| 02/25/2010 11:40 AM |
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But in my case, these variables must be declared as 'logic'.
Still, can I do something?
Tks Shalom! o/ |
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SHALOM
Posts:43
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| 02/25/2010 11:44 AM |
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Use 'real' temporary variables, then assign the 'real' results to the logic vectors.
Shalom |
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William
Posts:5
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| 03/02/2010 11:26 AM |
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Right...
now here's another problem... see the simple code below:
module SystemVerilog1();
real a;
always_comb begin
a = 3.5;
end
endmodule
Now, when I declare a 'real' data type and compile the code, an error is detected:
"real variable data type values are not supported"
What's worng now? Is this my Quartus or what?
Thanks again, Shalom! |
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SHALOM
Posts:43
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| 03/02/2010 1:05 PM |
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For synthesis or simulation?
Shalom |
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William
Posts:5
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| 03/02/2010 6:42 PM |
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For synthesis, Shalom.
I did not simulate it, because this code didn't even compile without errors... |
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SHALOM
Posts:43
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| 03/03/2010 12:13 AM |
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Well, real variables are not supported for synthesis.
Shalom |
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