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Subject: Declaration of a class within a module in System Verilog

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Chait

Posts:2

02/19/2010 11:02 AM
Hi, I have a rather basic question. I am trying to get hold of the actual place we need to put in class declaration and instantiation. Should the class be declared inside a module? How about instantiating the class? Thanks, Chaitanya

Chait

Posts:2

02/21/2010 5:53 PM
Hi, Most of the example codes i checked out, a class declaration is done in a seperate SV file and it's being instantiated within a program/module. Thanks.

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