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 SVUG Community Forum
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William
Posts:5
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| 01/21/2010 5:53 PM |
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If anyone could help me, I'd apreciate it.
I'm working on a program written in C language.
My question is: is 'real' data type in SystemVerilog equivalent to 'float' in C?
If it is, is there any prroblem to use 'real' when I'm doing testbenches?
Thank you!
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SAUMYA
Posts:1
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| 01/28/2010 9:13 AM |
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According to Systemverilog_3.1 ; real in sv equivalent to double in c
and shortreal in sv is equivalent to float in c,
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