 |
|
|
|
|
|
|
|
|
|
|
|
|
 SVUG Community Forum
|
|
| Author |
Messages |
|
Nikhil
Posts:1
 |
| 01/19/2010 7:54 AM |
|
Hi
I have a design that has mixture of SV and Verilog Files . can I include verilog files inside a package i.e
package my_pkg
{
`include my_file_1.sv
`include my_file_2.sv
.
.
.
`include my_file_10.v
}
and then import the pkg as
import my_pkg :: *
Is it permissable.
|
|
|
|
|
|
| You are not authorized to post a reply. |
|
|
|
ActiveForums 3.7
|
|
|
|
|
|
|
|
|
|
|
|
|
 |
|