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 SVUG Community Forum
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| Author |
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Gal
Posts:1
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| 01/03/2010 1:49 AM |
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Hi,
Question :
Once you started to evaluate a combinatorial always block, and one of
the signals in the sensitivity list changed, Do you have to re-evaluate
this always block from the beginning ?
Background:
Verilog language is vague in the following question, and left for tool's implementation. Does SystemVerilog scheduling semantics solve this question ?
I could not find a definition of "sensitivity list" in any of the standards, 1995 till 2008, and no strict definition when always blocks should be evaluated.
A signal may change as a result of this same always block (bad coding, right !) and by interleaving statements between two always/assign processes.
re-evaluation solves all race problems and gives deterministic behaviour to RTL code. Avoiding re-evaluation contradicts the standard to my humble opinion.
The question is about good old "always" but is still relevant for always_comb as well.
Regards,
GV
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