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Subject: SV variable types from Synthesis point of view

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Gaurang

Posts:7

12/22/2009 8:35 AM
Hi Cliff, I am new to SystemVerilog and I am interested in knowing how well SystemVerilog can work for Design. I got an obvious doubt regarding the new data types bit, int, byte, etc. (Coz these data types are said to have default/initial value 0!) I tried to search whether these constructs are synthesizable or not. Later, I read the paper published in 2006 by Mr. Sutherland : "A Proposal for a Standard Synthesizable Subset for SystemVerilog-2005:What the IEEE Failed to Define". The proposal in this paper is well justified. But, I could not find what exactly is the latest on what SV constructs are really supported for synthesis. So, I have two basic doubts: (1) Are these 2-state variable types synthesizable? If yes, is it advisable to use them for design? (2) Although the above mentioned varibles "seem to have" default values, we can't have this in actual hardware. So, does it mean that all the designs that involve some counting logic should have reset to have initial count value?? I hope you can appreciate my questions. Thanks, Gaurang

SHALOM

Posts:43

12/22/2009 8:39 AM
(1) Are these 2-state variable types synthesizable? If yes, is it advisable to use them for design? Yes, and many people think not. (2) Although the above mentioned varibles "seem to have" default values, we can't have this in actual hardware. So, does it mean that all the designs that involve some counting logic should have reset to have initial count value?? Yes. Shalom

Gaurang

Posts:7

12/22/2009 9:08 AM
Can anyone put more light on this?

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