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Subject: SystemVerilog Cross Coverage:: Is cross of cross possible? Any limitation?
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MayankUser is Offline

Posts:1

12/14/2009 12:22 AM  
Code -->
rand bit ⎛:0] x,y,a,b;
covergroup cg_xy @(posedge clock);
  X : coverpoint x;
  Y : coverpoint y;
  A : coverpoint a;
  B : coverpoint b;
  XY : cross X, Y;
  AB : cross A, B;
XA : cross XY, AB; // IS THIS ALLOWED ??
endgroup

Simulator -->
QuestaSim vsim 6.5c Simulator 2009.08 Aug 27 2009

karthikUser is Offline

Posts:12

12/15/2009 10:01 PM  
Hi Mayank,

This is not possible. Cross bin definition should only have covepoints or variables.
 
But you can use it like, to meet your requirement:

   XA: cross X, Y, A, B;


Thanks & Regards,
Karthik
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Forums > General Discussion > Main Discussion Area > SystemVerilog Cross Coverage:: Is cross of cross possible? Any limitation?



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