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 SVUG Community Forum
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| Author |
Messages |
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AMAL
Posts:24
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| 11/17/2009 4:08 PM |
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| I posted this on comp.lang.verilog as well:
Here is another frustrating missing feature in V2K and SV. I have a dilemma and it relates to the way attributes are defined in Verilog 200x and SystemVerilog. Basically I would like to attach an attribute to a declaration inside a module. The attribute could vary from instance to instance. I thought I use macro defines, but couldn't think of a way to do it per instance.
I don't want to start language wars again, but I DO NOT understand WHY simple features like this or so many other things that I can think of in VHDL is still not even supported in SystemVerilog!!!
Here is what I like to do in Verilog and be able to change attribute_1 and attribute_2 values per instance:
---start-verilog-code---------
module xyx;
// This
(* keep, attribute_1 = "value_1" *)
reg a;
// OR
reg b /* synthesis keep, attribute_2 = "value_2" */;
endmodule //:xyx
---end-verilog-code---------
In VHDL this is possible and pretty easy to do:
---start-vhdl-code---------
entity xyz is
generic ( attr1 : string := "value_1"; attr2 : string := "value_2" );
port (
ia : in bit;
oa : out bit;
ib : in bit_vector(1 downto 0);
ob : out bit_vector(1 downto 0)
);
end entity xyz;
architecture rtl of xyz is
signal a : bit;
signal b : bit_vector(1 downto 0);
attribute attribute_1 : string;
attribute attribute_1 of a : signal is attr1;
attribute attribute_2 : string;
attribute attribute_2 of b : signal is attr2;
attribute syn_keep : boolean;
attribute syn_keep of a : signal is true;
attribute syn_keep of b : signal is true;
begin
a <= ia; oa <= a;
b <= ib; ob <= b;
end architecture rtl;
---end-vhdl-code---------
I hope I did not not jump the gone, but it would be great if anyone can come up with an elegant solution.
-- Amal
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