I just learned that the modport_hierarchical_ports_declaration syntax from the Accellera LRM is
missing in the IEEE 1800 LRM. Without this feature it is not clear (at least to me) how one
could express hierarchical interfaces in a useful way. E.g:

interface part1;
logical foo, bar;
modport master(output foo, input bar);
modport slave(input foo, output bar);
endinterface

interface combined;
part1 p1(), p2();
modport master(p1.master, p2.master); // this is not allowed in the IEEE LRM
modport slave(p1.slave, p2.slave);
endinterface

module masters(combined.master m);
master1 m1(.m(m.p1));
master2 m2(.m(m.p2));
endmodule

Does anyone have any idea how to express this in a synthesizable way in
IEEE 1800 SystemVerilog ?

-stefan

Stefan,

This was a major issue during the IEEE balloting process. See http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0000629 (guest/guest)

The issue boils down to how the composition of the interface is seen from the master: Does it see the modport hierarchy, or are the nested modports promoted up with an OO-like inheritance? Ultimately, the committee could not come to consensus and took the feature out. It could be added back in once an agreement is reached, or it could be replaced with something completely different.

Today, you will have to use modport expressions to get the synthesizable code you are looking for.

interface combined;
part1 p1(), p2();
modport master(output .p1_foo(p1.foo), .p2_foo(p2.foo), input .p1_bar(p1.bar). p2_bar(p2.bar));
modport slave(input .p1_foo(p1.foo) .p2_foo(p2.foo), output .p1_bar(p1.bar), p2_bar(p2.bar));

endinterface

- Dave