Hi group

i am very new ti VMM.. i need to work on VMM in next project..i went thru some documents regarding VMM..i am not clear with the special features on it//and dow it is superior to system verilog..SV supports all type of automization..then how VMM differs..plz if anybody can tell me in brief this will be helpful for me to start up with VMM and can be familiarized with VMM befor starting of my project...

i hope the mebers of this group will spare little time and reply for my question..and also requests you to suggest any site for the beginners of VMM....waiting for the response from the grouip..hope u will not dissappoint me by not teplying..

thanks

vlsi engg

Hi,

    SystemVerilog is a language. VMM is methodology that ease the job of verification engineer in using the SystemVerilog for devleopment of verification environment.

    VMM will give users rules, recommendations and guidelines for quick and efficient verification environment for  verification of modules. By adopting VMM engineers can develop efficient verification environment in less time frame.

-Raja.

hi

thnx for ur reply..so vmm is just a methodology..

well thnx..in future i would trouble u if i face any difficulty..