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 SVUG Community Forum
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| Author |
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Juan
Posts:1
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| 07/09/2010 9:29 AM |
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Hello,
I am trying to determine whether a set of dynamic constraints (i.e., they are based on a couple of state variables that may change during simulation) I have placed inside a class in my testbench is over-constrained.
The only solution I have found so far is to invoke randomize() and test for its result but this produces a lot of "over-constrained class" output that I don't want.
Is there a different function I can call to check whether the class is over-constrained?
Another alternative I was considering (but so far unsuccessful) would be to re-direct the output temporarily to /dev/nul while I call randomize() and then restore it to stdout. Is there a way of doing this in SystemVerilog?
Any other suggestions/ideas would be greatly appreciated.
Cheers,
Juan |
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