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 SVUG Community Forum
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| Author |
Messages |
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Andrea
Posts:1
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| 10/17/2007 3:22 AM |
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Hi all,
Here's my problem: I am tryng to sample the data written to a SSRAM by saving them in a packed array. But it doesn't work.
The memory is split in 3 consecutive banks 128k x 32 each: bus data is 96 bits wide. New data and address is provided eack clock period.
Here is a portion of the code I wrote down:
These are the declarations:
logic �:0] ⎫:0] bank_0;
logic �:0] ⎫:0] bank_1;
logic �:0] ⎫:0] bank_2;
This is my initial:
initial
begin
//[setup_of the system]
while (sramwen)
begin
@(posedge clock);
bank_0[sramaddr] <= sramdata⎫:0]
bank_1[sramaddr] <= sramdata⏋:32]
bank_2[sramaddr] <= sramdata⏫:64]
end
end
The data actually written to those array are xxxxxxxx.
Somewhere there must be a silly mistake, I know...
Thanks. |
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Malvika
Posts:3
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| 11/03/2008 10:48 PM |
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your code is not clear some of the things are missing..
Please type it clearly |
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