Hello DM,
My short answer to your question is: no, no, yes.
But let me elaborate a bit, since you have a number of options here, and without more details it would be difficult to suggest the one you're looking for.
Firstly, you should be able to call verilog tasks and functions directly inside SV classes thru absolute hierarchical referencing from the top level module. This may not be supported though by all simulators at this point. Note that an SV class cannot itself contain a module instance.
An alternative is to put the verilog tasks inside an SV interface instead of a module, and have a virtual interface in any class that needs access to the tasks. The virtual interface is essentially a handle to a concrete interface; it is assigned an instance of a concrete interface at run-time.
Another alternative, and perhaps the easiest, is to just put your tasks directly inside a class (copy-paste). In all likelihood they will compile and are usable with little or no modifications inside the class context. Just beware of the fact that tasks and functions inside modules and interfaces are static by default, while in a class context they are automatic by default. You can readily change this using the automatic/static keywords.
Hans