Hello,
I have a query in what ways driver class to be implemented.
I referred some example in the SystemVerilog book(I have not referred all examples only few), in all the example I referred the driver class is implemented in the program block, the major reason what iam thinking for the driver class to implement in the program block is, the driver need to drive value to the DUT, and the DUT interface block will be visible to the Driver class since the program Test block will have the interface/DUT signal as an input, so using a task in the driver class we can drive/monitor DUT pins.
Driver class inside the program block
-------------------------------------
program test(and_gate_if_u and_gate_if);
class driver;
task drive
#10 and_gate_if_u.a <= 1’b0;
#10 and_gate_if_u.b <= 1’b0;
endtask
endclass
endprogram
What I wanted I need to implement the Drive class outside the program block i.e in a separate file inorder to make the class generic so that in all the program TEST I will make use of Driver class; in that case I will be using tasks to drive DUT signals, in that case since iam implementing the drive class outside the class how I will have the access to the interface block or the signal blocks in DUT?
To give a better idea of the above scenario I have given the code bellow,
Driver class outside program block
-----------------------------------
program test(and_gate_if_u and_gate_if);
initial
begin
driver d1;
d1 = new();
d1.drive
end
endprogram
Driver Class
------------
class driver;
task drive
// Here I need to drive and_gate module signal ‘a’ and ‘b’ how to drive
// Since this class is implemented in a different file the interface won’t
// visible to this driver class
endtask
endclass
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