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 SVUG Community Forum
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| Author |
Messages |
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Nithin Kumar
Posts:4
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| 12/07/2009 12:16 AM |
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Hi all,
I'm new with SystemVerilog and need your help.
When i run the following code output is coming in a different what i expected.
module asso_str_str;
string str[string]='{"sachin":"one","dravid":"two","ganguly":"three"};
string s ;
initial begin
foreach (str[s])
$display("string = %s and rank =%s",s,str[s]);
#10 $finish;
end
endmodule
Output is coming like this:
string = dravid and rank =two
string = ganguly and rank =three
string = sachin and rank =one
Can any body explain the the cause for this.Please let me know the cause.!!
Thanks,
Nithin |
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