Hi hvschoot,
Sorry I got confused because you used the word "synthesis". So, I guess synthesis wouldn't complain about XMRs and internal interface signals, then, right?
Also, you mentioned that you have to use assign statements to connect all interface instance signals to each other (and the top level). In my opinion thats not true,..... You could also achieve the same result by instantiating the interface only once, but using the same instance of that interface within all modules that use those signals,....
i.e.
interface ahb_if(); bit HCLK; bit HRESETn; ... endinterface : ahb
module ahb_master(ahb_if bus); ... endmodule : ahb_master
module ahb_slave(ahb_if bus); ... endmodule : ahb_slave
module top(); ahb_if ahb_bus(); ahb_master master1(ahb_bus bus); ahb_slave slave1(ahb_bus bus); ... endmodule : top
The above should achieve the same result, shouldn't it? Ofcourse if one wants to share signals between different interface instances of different interface definitions, then I guess one has to use interface ports.
Why should one instantiate a single interface definition more than once for applications like a bus, if the goal is simply to connect modules to each other using that interface/bus? (unless trying to model something like a multi clock domain design for an interface that is NOT a shared bus) |