The only user group created for SystemVerilog users is back with an exciting series of events! We need more user involvement to make these events even more valuable to all of you. Once you start going through the registration process, we will be asking you for participation in presenting short tips and tricks as well as submitting questions for the 'Stump the Experts Panel'. Get involved. After all the group was created by users for other users like you. Even if you are just getting started with SystemVerilog, we want to hear from you. Chances are there are many others like you.

SystemVerilog Users Group has a simple goal to advance the SystemVerilog language and encourage the adoption of associated tools, methods, and IP and help address areas where training is required. If you are a design or verification professional looking for a fun, informative way to keep on top of the SystemVerilog ecosystem, then you need to register for a fall user group meeting at one of the following locations:

These great locations will stimulate your SystemVerilog intellect with instructive tutorials and informative presentations, wonderful food & drink and best of all - the chance to mingle with your peers and the industries' top SystemVerilog experts.

Click the links above to view each location's agenda and schedule.

We'll see you there!

The only user group created for SystemVerilog users is back with an exciting series of events! We need more user involvement to make these events even more valuable to all of you. Once you start going through the registration process, we will be asking you for participation in presenting short tips and tricks as well as submitting questions for the 'Stump the Experts Panel'. Get involved. After all the group was created by users for other users like you. Even if you are just getting started with SystemVerilog, we want to hear from you. Chances are there are many others like you.

SystemVerilog Users Group has a simple goal to advance the SystemVerilog language and encourage the adoption of associated tools, methods, and IP and help address areas where training is required. If you are a design or verification professional looking for a fun, informative way to keep on top of the SystemVerilog ecosystem, then you need to register for a fall user group meeting at one of the following locations:

These great locations will stimulate your SystemVerilog intellect with instructive tutorials and informative presentations, wonderful food & drink and best of all - the chance to mingle with your peers and the industries' top SystemVerilog experts.

Click the links above to view each location's agenda and schedule.

We'll see you there!