SVUG - Cambridge, UK - October 9, 2007

Location

Homerton College
Ibberson Building
Hills Road
Cambridge CB2 2PH
(map)
01223 507218

Tutorials

2:00 - 2:30: Tutorial arrival & check-in

2:30 - 4:00: SystemVerilog for Verification -or- SystemVerilog Design Fundamentals

Presentations

4:00 - 4:30: User Group arrival & check-in

4:30 - 5:15: Functional Coverage in System Verilog

5:15 - 6:00: SystemVerilog FSM, Assertion & RTL Tricks for Design Engineers

Networking

6:00 - 7:00: Food, drink and networking.

View the presentations (.pdf) in the Members only Resources section.

Tutorial Authors and Abstracts

SystemVerilog for Verification
 
Presented by Hans van der Schoot, Mentor Graphics

Interest in the use of SystemVerilog for verification has been steadily growing since the language was standardized in 2005, and is getting ever stronger as more organizations are exploring a transition to SystemVerilog and open standards in general. This tutorial will be a concise tour of the state-of-the art verification features of the language, consolidating the following topics as the key to effective verification using SystemVerilog:

~ New SystemVerilog datatypes
~ Object oriented programming
~ Constrained random generation
~ Intelligent automated self-checking
~ Total coverage analysis
~ Coverage driven verification

SystemVerilog Design Fundamentals

Presented by Cliff Cummings, Sunburst Design, Inc.

This tutorial introduces engineers to new IEEE 1800-2005 SystemVerilog RTL and Behavioral Design enhancements to increase design & coding efficiency. This seminar will not provide a history of, or justification for the SystemVerilog language. It is assumed that engineers who attend already understand the importance of SystemVerilog and are interested in a quick introduction to its syntax and capabilities.

Presentation Authors and Abstracts

SystemVerilog FSM, Assertion & RTL Tricks for Design Engineers

Presented by Cliff Cummings, Sunburst Design, Inc.

How do designers get the most from FSM enumerated types? What are some simple tricks to help designers use concurrent assertions? What new SystemVerilog constructs have been added to help build robust and concise RTL designs? This presentation will show a few tricks from the experts to address these questions and help RTL designers get the most from new SystemVerilog features.

Functional Coverage in SystemVerilog

Presented by Jason Sprott, Verilab Ltd.

How do we choose between SVA cover properties and covergroups, and what are the advantages of each? How do we build coverage models to get meaningful results, and can we use those results to influence stimulus? This presentation addresses some typical Functional Coverage questions posed by design and verification teams, explains some of the decisions made, and demonstrates some of the techniques used by the experts on their projects.