SVUG - Austin, TX - October 17th
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Location
Cool River Cafe
4001 Parmer Lane
Austin, Texas 78727
(map)
512.835.0010
Overview
In addition to the presentations by industry experts during the user group meetings, we are also offering 2 tutorials. These tutorials will take place before the meeting in the same location and last about 90 minutes. Both start at the same time so you have to pick one or the other. They will be repeated at every SVUG meeting so if you don't have a chance to attend, there is always next time.
The goal is simple. If you are just starting to look at SystemVerilog, then the 'Fundamentals of SystemVerilog' is something you should not miss. This is a short introduction to the IEEE 1800-2005 SystemVerilog RTL and behavioral design enhancements to increase design and coding efficiency. The only prerequisite is previous experience with Verilog or VHDL. The second tutorial is a concise tour of the verification features of SystemVerilog. Prior knowledge of verification and Verilog will be helpful to get the most out of this tutorial.
Tutorials
2:00 - 2:30: Tutorial arrival & check-in
2:30 - 4:00: SystemVerilog for Verification -or- SystemVerilog Design Fundamentals
Presentations
4:00 - 4:30: Presentation arrival & check-in
4:30 - 5:15: Functional Coverage in System Verilog
5:15 - 6:00: SystemVerilog FSM, Assertion & RTL Tricks for Design Engineers
Networking
6:00 - 7:00: Food, drink and networking.
Tutorial Authors and Abstracts
SystemVerilog for Verification
Presented by Hans van der Schoot, Mentor Graphics
Interest in the use of SystemVerilog for verification has been steadily growing since the language was standardized in 2005, and is getting ever stronger as more organizations are exploring a transition to SystemVerilog and open standards in general. This tutorial will be a concise tour of the state-of-the art verification features of the language, consolidating the following topics as the key to effective verification using SystemVerilog:
~ New SystemVerilog datatypes
~ Object oriented programming
~ Constrained random generation
~ Intelligent automated self-checking
~ Total coverage analysis
~ Coverage driven verification
SystemVerilog Design Fundamentals
Presented by Cliff Cummings, Sunburst Design, Inc.
This tutorial introduces engineers to new IEEE 1800-2005 SystemVerilog RTL and Behavioral Design enhancements to increase design & coding efficiency. This seminar will not provide a history of, or justification for the SystemVerilog language. It is assumed that engineers who attend already understand the importance of SystemVerilog and are interested in a quick introduction to its syntax and capabilities.
Presentation Authors and Abstracts
SystemVerilog FSM, Assertion & RTL Tricks for Design Engineers
Presented by Cliff Cummings, Sunburst Design, Inc.
How do designers get the most from FSM enumerated types? What are some simple tricks to help designers use concurrent assertions? What new SystemVerilog constructs have been added to help build robust and concise RTL designs? This presentation will show a few tricks from the experts to address these questions and help RTL designers get the most from new SystemVerilog features.
Functional Coverage in SystemVerilog
Presented by Doulos, Inc.
Kevin Schott - Correct Designs
A Doulos Certified Training Provider
Everyone's talking about coverage driven verification, but how do you make it work in reality? This presentation links theory to practice by exploring the big verification questions that can only be answered by collecting coverage information, and by explaining how you can write SystemVerilog code to help answer those questions effectively and efficiently. We'll discuss the two forms of coverage that are new in SystemVerilog - covergroups and property coverage - and take a look at how current tools help you to display, manage and interpret the data that they yield.