SystemVerilog for Verification

Presented by Hans van der Schoot, XtremeEDA

Interest in the use of SystemVerilog for verification has been steadily growing since the language was standardized in 2005, and is getting ever stronger as more organizations are exploring a transition to SystemVerilog and open standards in general. This tutorial will be a concise tour of the state-of-the art verification features of the language, consolidating the following topics as the key to effective verification using SystemVerilog:

• New SystemVerilog datatypes
• Object oriented programming
• Constrained random generation
• Intelligent automated self-checking Total coverage analysis
• Coverage driven verification

SystemVerilog Design Fundamentals

Presented by Cliff Cummings, Sunburst Design, Inc.

This tutorial introduces engineers to new IEEE 1800-2005 SystemVerilog RTL and Behavioral Design enhancements to increase design & coding efficiency. This seminar will not provide a history of, or justification for the SystemVerilog language. It is assumed that engineers who attend already understand the importance of SystemVerilog and are interested in a quick introduction to its syntax and capabilities.