SVUG has a simple goal to advance the SystemVerilog language and encourage the adoption of associated tools, methods, and IP and help address areas where training is required. Participation in the group is an excellent way to receive technical content, education, meet with your peers, and get exposed to SystemVerilog gurus.

In addition to user group meetings which will be held at various technology hubs around the world, the SVUG website offers multiple ways to continue networking online. There are news updates, discussion forum, resources, and information on upcoming events.

If you are a design or verification professional looking for a fun, informative way to keep on top the SystemVerilog ecosystem, SVUG is the place to be. It is the only user group entirely dedicated to SystemVerilog. Becoming a member is simple and free. Simply join and expose yourself to SystemVerilog today!